For CMOS processes, the min length for a MOSFET (Lmin), the oxide thickness (tox), and the typical supply voltage (VDD) all track each other. They all go down together with smaller dimension processes. Below 130nm, things get wierd. For these processes, tox may even go up, and VDD levels out at about 1V. Although in some cases, the process is designed to work with a VDD > 1.0V to achieve higher speeds.
For an excellent discussion of how and why this parameters track each other, see this paper by Berkeley Prof. Chenming Hu, "Gate Oxide Scaling Limits and Projection".
For quick reference, here is a table Lmin, VDD typ, & tox for some typical CMOS processes:
Lmin (nm) VDD typ. tox (nm)
500 5.0 11.0
350 3.3 6.6 ,7.0, 8.5
250 2.5 4.8, 5.0
180 1.8 3.0, 3.2
130 1.2 2.0
90 1.0 2.3
65 1.0 2.6
